LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY divider_test IS
END divider_test;
 
ARCHITECTURE behavior OF divider_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT div_base_4
    PORT(
         clk : IN  std_logic;
         start_division : IN  std_logic;
         numerator : IN  std_logic_vector(31 downto 0);
         denominator : IN  std_logic_vector(31 downto 0);
         quotient : OUT  std_logic_vector(31 downto 0);
         remainder : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal start_division : std_logic := '0';
   signal numerator : std_logic_vector(31 downto 0) := (others => '0');
   signal denominator : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal quotient : std_logic_vector(31 downto 0);
   signal remainder : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: div_base_4 PORT MAP (
          clk => clk,
          start_division => start_division,
          numerator => numerator,
          denominator => denominator,
          quotient => quotient,
          remainder => remainder
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

		-- TEST 1a: 12345678h / 3h = 6117228h
		numerator <= x"12345678";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1b : 12345679h / 3h = 6117228h + 1h
		numerator <= x"12345679";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1c : 1234567Ah / 3h = 6117228h + 2h
		numerator <= x"1234567A";
		denominator <= x"00000003";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1d : F000BEAFh / F000BEAFh = 1h + R 0h
		--- Divide by itself
		numerator <= x"F000BEAF";
		denominator <= x"F000BEAF";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1e : 0A0B0D19h / 0A0B0D1Ah = 0h + 0A0B0D19h
		--- Divide by itself
		numerator <= x"0A0B0D19";
		denominator <= x"0A0B0D1A";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1f : 01010102h / 00000000h = DIVIDE BY ZERO - need to handle.
		numerator <= x"43741FEA";
		denominator <= x"00000000";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
		-- TEST 1e : AAAABBBBh / 11119876h = 9h + R 110c5f95
		numerator <= x"AAAABBBB";
		denominator <= x"11119876";
		wait for clk_period;
		start_division <= '1';
		wait for clk_period * 1;
		start_division <= '0';
		wait for clk_period * 20;
		
      wait;
   end process;

END;
